الفهرس 
Open Coherent Accelerator Processor Interface (OpenCAPI)
Functional VerificationOnly 14 pages are availabe for public view
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Abstract
As the applications that requires huge memory increases, there is a need to provide storage access with lower latency in addition to cache coherency between processors as a host and storage units. The availability of cache-coherent “far” memory protocol like Compute Express Link (CXL) provided an opportunity regarding memory subsystems.
This thesis proposes a novel architecture for the transaction and data link layers of CXL, as defined in CXL specification revision 2.0. It focuses on implementing the concerned layers as described in CXL memory protocol specifications inside a host side. CXL is a multi-protocol technology designed for supporting memories and accelerators. It provides a set of protocols including different semantics such as I/O protocol similar to Peripheral Component Interface Express (PCIe), caching protocol, in addition to memory device access protocol. It works over an on-package or discrete connectivity.
An architecture is presented containing both transmission and reception chains. It en- sures a reliable conveyance of the packets across two CXL units using the CXL protocol. This thesis interprets by what method the implementation maintains the dependably conveying of data, responses and requests, through appending each transmitted flit by a 16-bit Cyclic Redundancy Check (CRC), and how the received packets are being pro- cessed. The proposed architecture is intended to have simple implementation in addition to having minimum data path delays.
The whole architecture is designed using verilog HDL. Then, it is verified using developed verilog checkers inside the test-benches for different protocol scenarios. The results are compared with the reference sequences provided by the standard to make sure that the functionality of the system is achieved. Both the reference sequences and the simulation results are presented.
A setup for assessment of the architecture is also built to provide sensible estimation of performance and cost in both ASIC and FPGA platforms. In ASIC performance evaluation, the proposed hardware implementation is synthesized using UMC 130 nm and TSMC 28 nm technologies to get the maximum achieved frequency and calculate the corresponding power and area. It manages to work up to 1 GHz using TSMC 28 nm technology and 438.59 MHz using UMC 130 nm technology. Its estimated dynamic and leakage power consumption by UMC 130 nm technology at 1 GHz are 95.3698 mW and 171.17 mW respectively. In addition, its area cost extracted after synthesis is 242 124.8 µm2. While in FPGA, 470.8 MHz is the maximum frequency on Kintex UltraScale FPGA board which the design can operate at. It consumes most of the IOs on this FPGA board and less logic circuits.