الفهرس 
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Abstract
With the evolving of processors and the rise of multi-core processing sys-tems, additional requirements are placed on the memory system to provide adequate service of references that does not hinder the potential performance improvements these systems can offer. This adds to the memory controller the responsibility of keeping up with the increased core speeds by paralleliz-ing memory references in order to mitigate the effect of the slower DRAM cores. While providing a good balance between the fairness of service be-tween competing threads and maximizing system throughput. This increas-ingly challenge the design of memory controllers where to-date scheduling policies strive to solve the fairness vs throughput requirements of multi-core systems.
Self-Optimizing Memory Controllers present a great potential in the future of memory controllers. As they alleviate the burden of designing an optimal memory scheduling policy, while providing adaptability to different work-loads and systems. Previous state-of-art controllers scheduled memory ac-cesses on the command level. This causes the agent to lose sight of the rela-tion between commands and can lead to the issuing of unuseful sequences of precharge/activate of rows or closing banks that should have been left open, and vice versa. In this work we propose a bank-aware self-optimizing memory controller that schedules memory references on the request level, presenting to the agent the actual problem it needs to tackle. This simplifies the evaluation of system attributes and eliminates the need for correction mechanisms that was needed in previous controllers. With the proposed algo-rithm a maximum of 18% increase in the data bus utilization is achieved compared to the commonly used FR-FCFS algorithm.
RL online training capabilities represent an optimal solution to this problem where the RL memory scheduler can adapt to the changing thread combina-tions feeding the system and learn to take better scheduling decisions that best fit the optimization target. This elevates the designer responsibility from defining system thresholds to analysing the potential root causes of schedul-ing biases and defining the correct optimization target.