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Abstract
This thesis presents a new compact model for Double-Gate Tunnel Field-E{uFB00}ect Transistor (DG TFET). This physically based model accounts for the tunneling at the source channel interface as well as for the drift-di{uFB00}usion in the channel region. It also accounts for the ON and the subthreshold modes of operation. This model enables the calculation of the I-V, Q-V and C-V characteristics of the device. The model is validated by comparing its results with that calculated numerically by the Sentaurus device simulator