الفهرس 
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Abstract
VLSI thermal analysis and management mechanisms have become more critical for SoCs performance and yield. Especially with the growing complexity in design requirements and manufacturing process, more physical, circuit and reliability checks are needed to accomplish tape-out with faster turn-around time (TaT) and better quality of results (QoR). Thermal issues are more commonly manifested as soft/out-of-specification failures. Not only these soft failures tend to alter the carrier mobility, clock timing delays, leakage power and electrical matching requirements, but also it creates reliability issues such as mean-time-to-failure (MTTF) and aging phenomenon such as bias temperature instability, time-dependent dielectric oxide breakdown, and electromigration.
Traditional thermal/power analysis mechanisms started as post-silicon point-contact thermocouple or infrared imaging processing that took place on the fabricated chip specially on the packaging level which do not give actionable feedback to the designers. This led to a very expensive thermal fixing and controlling mechanisms of reimplementing the whole design in an iterative process. Pre-silicon thermal analysis mechanisms are either design-, placement-, or electrical-based techniques: design-based techniques, such as clock and power gating, are digital domain oriented and usually require bulky on-chip thermal control circuits. Placement-based techniques are not standardized and tied to specific design environments while the electrical-based techniques provide early and actionable feedback to designers.
The challenges in the electrical-based thermal analysis are not only related to the complex electrothermal modeling, but also that they need larger database that consolidates geometrical, electrical, and thermal information. Advanced database management and parallel processing techniques are continuously evolving to cope with the exponential growth in data size. However, it is essential to optimize the input data itself by pivoting on the VLSI aspects. This gives rise to the need to design, simulate and verify the whole system after decomposing (partitioning) it into smaller subsystems and rebuilding its database bottom-up (clustering) based on optimized and electrical-aware data. Various partitioning-clustering mechanisms are invoked for every design phase. Iterative graph-based partitioning mechanisms used in circuit simulators have low parallelization capabilities. On the other hand, cell-based (hierarchical/agglomerative), template-based (clip/density) and pattern-based partitioning mechanisms scale better on multiple threads, but they are limited to geometrical processing such as design rule checking and lithography simulations respectively. Recent partitioning mechanisms use functional- and electrical-driven partitioning to fulfill advanced verification requirements.
This work proposes a new thermal verification flow that leverages an electrically aware partitioning-clustering data mining scheme. This scheme adopts a signature-based approach for database optimization inspired by analog DFT signature techniques. The proposed flow demonstrates the database compression QoR, EoU and TaT of a low noise amplifier block. Moreover, it allows for extended reliability checks which are later used to drive a thermal management technique that allows for resolving thermal hotspots, thermal symmetry mismatches, and smoothens the thermal gradients. The results are compared to the state-of-the-art techniques in literature on blocks with similar size and complexity.