الفهرس 
MotivationOnly 14 pages are availabe for public view
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Abstract
Recently, low-power circuit design gains a big momentum as it considered as a key enabler for different applications, especially Internet of Things (IoT) systems. Moreo-ver, low-power circuit design allows reducing the battery size by reducing the needed power consumption, which accordingly reduces the area/cost of these systems and enhance the battery lifetime. Typically, the receiver (RX) and the Transmitter (TX) within the wireless communication systems consume a significant fraction of power from the whole power consumption. Phased Locked Loop (PLL), which is a basic building block in any wireless communication systems for a precise clock generation, dominates the power consumption of the RX/TX. Moreover, the frequency divider and the Voltage-Controlled Oscillator (VCO) within the PLL dominates the power consumption of the PLL.
Consequently, in this thesis, a low-power, low area Phased Locked Loop is presented using 130nm CMOS technology. The proposed frequency synthesizer exploits the charge steering concept within the VCO and the frequency divider to reduce the pow-er consumption of the entire PLL. The proposed PLL system is suitable not only for low-power systems but also for low supply voltage applications.
Charge steering based circuits are then implemented and designed to get an output frequency of 2.4 GHz from a 100 MHz reference signal. Simulations show a total power consumption of only 0.13 mW from a 1-V supply in 130nm CMOS tech-nology. The PLL achieves a phase noise of -110 dBc/Hz at 1-MHz offset from the carrier signal, 2.4-GHz. The total root-mean-square jitter, rms, in a frequency range of (10KHz to 40MHz) is 1743 fs, which yields a figure of merit (FOM) of -244dB.