الفهرس 
chapter 1Only 14 pages are availabe for public view
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Abstract
In this thesis, novel circuit techniques for either increasing the speed or reducing the power consumption of digital MOS integrated circuits are presented. These techniques can be divided into five fronts. On the first front, novel circuit techniques are presented to enhance the performance of domino CMOS logic circuits. On the second front, novel circuit techniques are presented to speed-up CMOS circuits containing a stack of NMOS or PMOS transistors. On the third front, a proposed connection is presented to enhance the performance of pass-transistor logic circuits by connecting the substrate of the pass transistor to the output node. Also, a quantitative study is presented that decides on the optimum size of the bleeder transistor in order to optimize the performance. On the fourth front, two novel circuit techniques are proposed to enhance the performance of digital CMOS circuits. Finally, on the fifth front, three novel readout methods are proposed to read dynamic-random access memory (DRAM) cells with a read access time smaller than that of the conventional readout method.